Scor­pio News

Some time ago [1] I wrote on aspects of the Z80 microcomputer’s interrupt structure. In the article, I dealt mainly with the Z80 PIO. Since then there have been many requests for another article to deal with the other Z80 family chips. In this and a subsequent article it is my intention to cover the intricacies of programming the following chips:

Fortunately, the DART is a reduced specification SIO, providing only the asynchronous facilities, so for brevity I will simply refer to the SIO, and in general the DART will also be implied.

For ease of understanding, I propose to discuss the CTC/​SIO pair as used on the MAP CPU and MAP MPI boards. On these boards the CTC/​SIO group provide a most powerful, fully programmable, serial input/​output unit. This is not the only possible use for these chips, but it will serve well as an introduction, besides being the most common configuration for them.

Serial I/O interconnections have been very adequately dealt with in [2] and [3], and interested readers are referred to those articles for detail coverage of the subject. For the newcomer, it is appropriate to give a minimum explanation to set the scene. A Serial I/O chip is one which is given a byte of data and which squirts it out bit by bit onto a pair of wires – rather like a lump of dough being fed through a spaghetti maker – our new improved modified spaghetti maker which makes only one strand at a time! That is the act of transmission. Such a chip is also capable of receiving the individual bite of data and reassembling them into a byte – scrunching up all the fresh spaghetti to end up with a lump of dough again. There are other concerns, which need not affect us here, such as level shifting from TTL levels (0-5 volt) to RS232 levels (+/– 12 volt), as these problems are dealt with in the articles cited.

If we imagine that we have a spaghetti maker at one end of a table manufacturing a single strand of spaghetti, and a reverse spaghetti maker at the other, we can hove pieces of dough from one end of the table to the other by feeding the output of one machine into the input of the other. It is easy to see that if the generator makes the spaghetti faster than the other machine consumes it, we will soon have a big pile of spaghetti on the table. If the consuming machine consumes faster than the maker, then the strand of spaghetti keeps getting pulled tight end breaking. So it becomes obvious that both machines must work at the same pace. Similarly when transmitting data from one serial device to another, they must both work at the same rate, or in jargon, be ‘clocked at the same rate’. One of the major problems with serial communications is finding the rate of transmission or reception, loosely called the ‘baudrate’. We will consider the use of a CTC to provide differing baudrates or ‘clocks’ for an SIO.

The CTC chip is a 28 pin member of the Z80 family. It comprises four channels, which are substantially the same. Addressed as four I/O ports, one for each channel, it can return an interrupt vector from each channel on the occurrence of certain conditions, which criteria can be programmed into that channel. For ease of reference, we number the channels from 0 to 3. Channel 0 differs from the others in that it remembers the interrupt vector for channel 0, and the onboard circuitry of the CTC is able to modify this interrupt vector to indicate the interrupting channel. This we will deal with shortly. Channel 3 differs from the other channels in that it (due to limitations of pin numbers) cannot output pulses, it can only count them.

The manual for the CTC [4] says that the CTC can be configured as a counter or as a timer. This is true, but confusing. I find the following picture easier to grasp: each channel of the CTC is a counter. The channel can be set up to count pulses arriving on the input pin for that channel (CLocK/​TRiGger input, CLK/​TRGn, where n refers to the channel number), or to count pulses arriving