Nascom News­let­ter

Principle.

The EPROM is emulated by a 2K by 8 bit block of RAM. The data and address lines of the RAM are accessible both by the target hardware and by the host computer, in our case a Nascom. The host can read or write to the memory but the target system can only read.

When the target system is accessing the RAM, the host is switched off and is unable to affect the emulator. When the host is in control, the target system cannot access the RAM.

In order to simplify the address line switching, the host addresses the RAM via a binary counter. The drawback is that the RAM locations must always be addressed in sequence. In practice, this is not a problem as the entire emulator is loaded quickly from an image in the Nascom memory.

The resulting hardware​is, therefore, simple and cheap, yet able to perform a function normally requiring expensive and specialized equipment. (Commercial emulators usually have their own CPU and I/O devices. In the unit described here, the monitor functions already present in the Nascom are used instead.)

Circuit Description.

Referring to the schematic diagram, ICs 8 to 11 form the 2K emulator memory. Since each chip is a 1K by 4 bit memory, they are arranged as two pairs, ICs 8 and 10 form the first 1K block and 9 and 11 the second. Address lines A0 through A9 are common to all 4 chips whilst A10 selects the block to be accessed, by driving the Chip Select lines via an inverter. (Part of IC 6). Two NAND gates (half of IC 7) are also included in the Select lines to allow the host computer to control them.

The 11 address lines are then multiplexed between the computer and the target system by ICs 2, 3, and 4. (74LS244 tri-state, non-inverting buffers.) Each package contains 8 buffers grouped in sets of 4, hence IC 3 is split ‘in half’ to provide the necessary configuration. One buffer is spare from each half of IC 3. Note – one of these is used up later on to control the output buffer, IC 5.

The Output Enable lines (pins 1 and 19) of the sets of buffers are connected by an inverter (again part of IC 6) so that only one set may be enabled at one time. The line called SWITCH performs this function and is under control of the Nascom along with the other control lines.

When SWITCH is LOW, the address lines from the target system (via SKT 2) are able to address the RAM. when SWITCH is HIGH, these inputs are turned off and the outputs of IC 1 drive the address lines instead.