Testing is quite simple, I found. It’s a matter of fitting
the WAIT – GATE with all the WAITs (M1 and R/W) in operation,
giving a normal and average cursor flash rate. This is followed
by setting to no WAITs, which gives a noticeable change of
cursor rate. A further test of M1 WAITs only, gives an increase
in cursor rate, but lees noticeable. (In almost all systems the
NAS-SYS ROM and workspace RAM will work without WAITs). Any
poor connections of the wire wrap sockets will show up as faults
in other sections of the Nascom circuit. These include the RESET
switch, single step logic, PIO, and serial interface. The manual
explains this, and these functions should be watched during
first operations:
Table 1. Switch Data
| SWITCH No. | Block | Cycle Type |
|---|
| 1 | A (ROM) | M 1 |
| 2 | A (ROM) | R/W |
| 3 | B (RAM) | M 1 |
| 4 | B (RAM) | R/W |
Table 2. Memory Device Timing
| Wait State Type | Memory Access Time |
|---|
| None | <275ns |
| M1 Only | <400ns |
| Full (M1 & R/W) | <525ns |
Using the above tables, the latter section of the manual
explains how the switches in Table 1 are used to provide each
ROM and RAM speed in Table 2. Switches 1 and 2 are set for ROM;
3 and 4 for RAM. If an access tine of < 400ns and > 275ns is
required for ROM and < 275ns for RAM, the switches should be set:
| ROM | RAM |
|---|
| 1 UP | 2 DOWN | 3 DOWN | 4 DOWN |
| M1 | NO R/W | NO M1 | NO R/W |
The main idea behind the WAIT – GATE, says the manual, is:
“In most systems only some memory access cycles actually
need WAIT states. The WATT – GATE circuit provides a flexible
means of controlling WAIT states so that the number of
unnecessary WAIT states is minimised. This can result in a
considerable increase in C.P.U. speed.....”
This I must agree with, when you consider that by far the most
frequently used operations are the reading and writing of the
memory, both ROM and RAM.