A REVIEW OF WAIT – GATE

by M.S. Smith

“What is WAIT – GATE” ? I hear you all ask. Well, you should have a good idea if you have studied memory “ WAIT – STATES ” in general, or in particualar, for Nascoms. For those of you who have not done so, I will now try and explain.

The Nascom 2/3 has facilities for driving RAMs and ROMs of varying access time. This entails providing WAIT – STATES by the use of the Z80 control line WAIT. The effect of WAIT is to give extended memory access cycles, allowing the use of slower memory devices. On the Nascom with WAIT enabled, this is done to every memory access cycle, ROM, or RAM, of the CPU.

Now for the important bit – what the WAIT – GATE can and cannot do for you, and how all this is achieved. With the WAIT – GATE the following are provided: an explanatory booklet / user manual, and benchmark test programs, the results of which will follow later. The first section of the manual explains how the device works, and what it will provide. It then goes on to describe the fitting, testing, and operation, finally concluding with a section on how to use it to best advantage. The clearly written manual and neat, well designed WAIT – GATE are easy to understand , and almost foolproof. Anyway, I didn’t find any information lacking or failure in the device.

Basically, the WAIT – GATE works by selecting how long a WAIT is necessary for both RAMs and ROMs. That is, if your memory devices do not require the full amount of WAIT, (ie. less than 525ns access time), which for RAM is usually the case these days. Or, if your RAM and ROM work at different speeds, the gate can be hardware – selected to vary the length of WAIT for each. Not every memory device needs wither no WAIT or full WAIT, but for 300 – 400ns devices, a WAIT on M1 cycles will suffice.

Fitting the device requires the removal of two IC’s (8 & 18) from the Nascom main board. The WAIT – GATE has two wire – wrap sockets for insertion into the now vacant sockets, in a. “piggy back” arrangement. The means that a gap above IC8 and IC18 of a sockets’ width should be available. The usual set up for Nascoms that I have met, is for the main board to be uppermost, so this should be no problem at all. Once in place testing can begin.

The WAIT – GATE has a “four DIP” switch and associated selector to choose which WAIT states are implemented. The RAM and ROM sections can be individually selected for either M1 and R/W (full) or M1 only; or for neither WAIT, as required. This dives all the combinations of WAIT.