Another Clock

By Rory O’Farrell

The article by Mr. G. Kirby in Micropower Vol 2 No 3 on a Real Time Clock was most interesting. As readers buses are getting more and more populated, it might be advisable to consider adding an output buffer to his circuit, as the 58174 chip does not have the high output of a bus driver chip. Those who are daunted by the prospect of wiring up a board to plug into the bus might like to try another approach.

This approach is to hang the 58174 on the PIO, in a very similar circuit. Due to the slow speed of the RTC chip, it is possible to drive it from the port lines, at the expense of rather complicated software, although it is now possible to use the clock on an unexpanded Nascom. I have been using this circuit for nearly a year and have modified much of my software to read the clock.

The circuit diagram is simple enough, but a few points might bear comment. The CS (Chip Select) line is inverted using a CMOS inverter, which is also driven from the standby battery in power down mode. The effect of power down on the chip (without the inverter) seems to be to place a low level on CS, NRDS and NWDS. For some reason, this results frequently in loss of time. Adding the CMOS inverter means that the external low level of the PIO on power down is transmitted to the 58174 chip as a high level, not enabling the chip, thereby preventing time loss. In addition to the three control lines I have detailed, there are four address lines and five data lines. These are connected up to the two ports of the PIO.

To Port A are connected lines as follows:
Bit A0 – DB0 pin 7
Bit A1 – DB1 pin 6
Bit A2 – DB2 pin 5
Bit A3 – DB3 pin 4
Bit A4 – pin 13 (interrupt line)

To Port B are connected
Bit B0 – AD0 pin 12
Bit B1 – AD1 pin 11
Bit B2 – AD2 pin 10
Bit B3 – AD3 pin 9
Bit B4 – NWDS pin 3 (Write Strobe)
Bit B5 – NRDS pin 2 (Read Strobe)
Bit B6 – CS pin 1 (inverted Chip Select)

I do not give the connections for the Nascom, as they differ between N1 and N2s. They can easily be read off the circuit diagrams.

CMOS is sensitive to certain powerdown conditions, which