Micro­power

Mhz clock. The clock can be controlled from an external crystal, or from an internal oscillator, and is available to the rest of the system. Refresh is provided by the chip; software can select the interval between successive refreshes, or even suspend it entirely!

The on-chip memory management unit provides for a flexible memory structure, by allowing dynamic page relocation, as well as write protect features. The 16 address lines output by the CPU are transformed into 19 bit physical addresses. This large cache of memory will facilitate multiple users (as for example, in schools), or foreground/​background processing (playing Adventure and monitoring the nuclear power plant at the same time!).

Delivery of the new CPU is not expected until the first quarter of 1983, and a price has not yet been quoted. It should be stressed that the chip will not be pin-forpin compatible with the Z80. however, it should not be impossible to make a very compact interface board, although until detailed pinouts and bus timings are published this can only be a dream. If the promise is kept of full software compatibility with the Z80, and three to five times the throughput with the same speed memory, then this will be quite some chip!